The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium is the premier international conference in Asia-Pacific region to share the recent progress of design, modeling, simulation and measurement related to the electrical issues arising at the chip, package and system levels. Covering the paper presentations, industry exhibitions, workshops and tutorials, EDAPS 2024 will be held at the Taj Yeshwantpur, Bangalore, India, December 17-19, 2024.

Papers should be submitted electronically in two-column and three-page PDF file format through the EDAPS website (www.edaps.org). A Microsoft Word template is available on the symposium website. Hardcopy submissions will NOT be accepted. Submitted manuscripts should be camera ready and compliant with the general standards of the IEEE, including appropriate referencing. Non-compliant manuscripts will not be considered for review.

DEADLINES

1. Prospective authors should submit a three-page manuscript by August 31, 2024 September 30, 2024.
   
2. Notification about acceptance will be given by October 21, 2024.
   
3. Accepted papers will be reproduced as-is in the Conference Proceedings.

For a PDF version of the call for papers, please click here.

The symposium will consist of oral and poster presentations. In addition, a number of prominent experts will be giving keynote lectures and tutorials on areas of emerging interest. The official language is English.

Conference Topics

1. 3D-ICs/TSVs/Interposers
2. Testing on 3D-IC and SiP
3. Signal and Thermal Integrity
4. Power Integrity and Power Distribution Networks (PDNs)
5. Computational Electromagnetics and Multi-physics Modeling
6. Thermal Management for 3D-ICs and SiP
7. Design/Modeling of High-speed Channels and Interconnects
8. High-Speed Wireline Communication
9. Jitter Analysis and Modeling Algorithms
10. Time/Frequency Domain Measurement Techniques
11. Power Supply Induced Jitter
12. Nanoelectronics for 3D-ICs and SiP
13. Machine Learning Applied to Packaging
14. Active Devices and Circuit Modeling Technologies
15. Electronic Packages, SiP/SoP
16. IC and Package Level EMC
17. Antennas in Packages (AiP)
18. RF/mm-wave and THz Packages
19. Miniaturized and Embedded Passives
20. Power Electronic Packages
21. Advanced Simulation Tools and CAD
22. Substrate Technology for Packages and PCBs
23. Electrical Design of Flexible Devices and Sensing
24. 2-D Materials for 3D-ICs and SiP
25. 3-D ICs and SiP Reliability
26. Electrical Design for 5G Wireless Communication
27. SI/PI Analysis of High-Speed Channels
28. Others

Deadline: September 30, 2024

Submission Format: 2 column, 3-page, PDF format only.

Submitted manuscripts should be camera ready and compliant with the general standards of the IEEE, including appropriate referencing. Noncompliant manuscripts will not be considered for review.

Location: Taj Yeshwantpur, Bangalore, India

Exhibits: EDAPS-2024 will be exciting forum for vendors to demonstrate their state-of-the-art-tools to the attendees. Interested vendors can contact the conference administration for more details.

For more information, please contact: admin@edaps.org