The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium has been one of the main events in the Asia Pacific region with a focus on the electrical design of chip, package and systems for electronics applications. For more than a decade, this symposium has attracted world class researchers from both academia and industry to share their state-of-the-art results in chip, package and printed circuit board design and measurements.
- Prospective authors should submit a three-page manuscript by
August 5, 2019September 15, 2019
- Notification about acceptance will be given by September 30, 2019.
- Accepted papers will be reproduced as-is in the Conference Proceedings.
- In addition, authors of accepted papers will be invited to submit an extended version of their manuscript for a Special Section based on EDAPS-2019 to be published in the IEEE Transactions on components, packaging and manufacturing technology (T-CPMT).
For a PDF version of the call for papers, please click here.The symposium will include both oral and poster sessions. In addition, a number of prominent experts will be giving keynote lectures and tutorials on areas of emerging interest. The official language is English.
- Testing on 3D-IC and SiP
- Signal and Thermal Integrity
- Power Integrity/Power Distribution Networks (PDNs)/Ground Noise
- Computational Electromagnetics and Multi-physics Methods for SI/PI/TI Analysis
- Thermal Management Design for 3D-ICs and SiP
- Design and Modeling for High-speed Channels and Interconnects
- High speed serial links jitter budgeting
- Jitter segregation algorithms and tools
- Time / Frequency Domain Measurement Techniques
- Power supply induced jitter and transfer functions.
- Nanoelectronics for 3D-ICs and SiP
- Machine Learning applied to packaging
- Active Devices and Circuit Modeling Technologies
- Electronic Packages, SiP/ SoP
- IC and Package Level EMC
- Antennas in Packages (AiP)
- RF/mm-wave and THz Packages
- Miniaturized and Embedded Passives
- Power Electronic Packages
- Advanced Simulation Tools and CAD
- Substrate Technology for Packages and PCBs
- Electrical Design of Flexible Devices and Sensing
- 2-D Materials for 3D-ICs and SiP
- 3-D ICs and SiP Reliability
- Electrical Design for 5G Wireless Communication
- DDR’s Signal and Power integrity considerations
STUDENT TRAVEL GRANTS ‐ A limited number of travel grants will be provided to support students of accepted papers. Selection will be based on papers submitted and requires paper presentation by the student at the conference.
August 5, 2019 September 15, 2019
Submission Format: 2 column, 3-page, PDF format only.
Submitted manuscripts should be camera ready and compliant with the general standards of the IEEE, including appropriate referencing. Noncompliant manuscripts will not be considered for review.
Location: Kaohsiung, Taiwan
Exhibits: EDAPS-2019 will be exciting forum for vendors to demonstrate their state-of-the-art-tools to the attendees. Interested vendors can contact the conference administration for more details.
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