Keynote Presentations

Keynote I

Unleashing the power of Advanced Packaging by connecting System Design Optimization and Smart Manufacturing.

Pradeep Vempaty,

Micron



Pradeep Vempaty currently is a Senior Manager, Product Development Engineering (PDE) in Micron Technology Operations India and based out of Hyderabad. He is currently managing digital twins, package design, integration, process control systems, package development product engineering and packaging characterization teams working towards delivering advanced packaging commitments and growing talent. He is extensively involved in Micron’s drive to advance the packaging expertise & experience of the talent pool in the region. He is working with Micron leadership, technical experts and universities in delivering credited courses, workshops in SEMI, and collaborating in establishing ATMP training centers for skilling and workforce requirements for semiconductor manufacturing and packaging. Joining at the early days of PDE in India, he managed the Process Design & Simulation team and had grown this team towards generating simulation or digital twins and raking recognitions, external publications and patents. Pradeep has Masters in Solid Mechanics & Design from IIT Kanpur and Bachelors from JNTU, Hyderabad with University Gold Medal.

Keynote II

Assessing the Risk of Chip-Package Interaction Failures in Advanced Packaging: Modeling Crack Initiation and Growth in BEOL Structures.

Chung-Shuo Lee, Ganesh Subbarayan,

Purdue University

Abstract - Heterogeneous Integration (HI) provides a powerful and cost-effective means for building complex systems. Recently, sophisticated examples of heterogeneously integrated packages containing nearly 50 dies, many fabricated by different vendors on different technological nodes, have been demonstrated. In general, 2.5D integration of many dies on a common substrate, or their complex 3DHI integration requires the use of a challenging combination of materials with interfaces that are potential locations for increased thermal resistance and mechanical fracture. The complex packages are in general at an increased risk of chip BEOL fractures due to mechanical interaction with the package. In this talk, I will describe computational approaches for modeling fracture in back-end-of-line (BEOL) structures. I will begin with analysis using classical elasticity theory for singular stresses at multimaterial junctions. I will then describe computational approaches to enriching the underlying domains with the singular stresses to calculate the generalized stress intensity factor at multimaterial junctions, and as a special case, stress intensity factors at crack tips. I will next describe the concept of a configurational force as a generalized, thermodynamically consistent approach to modeling initiation and growth of cracks. Finally, I will demonstrate several examples of crack initiation and growth in BEOL structures.

Ganesh Subbarayan is the James G. Dwyer Professor of Mechanical Engineering at Purdue University and the Co-Director of the Purdue-Binghamton SRC Center for Heterogeneous Integration Research in Packaging (CHIRP). He also serves as the Director of the recently created Atalla Institute for Advanced System Integration and Packaging (ASIP) at Purdue University. He began his professional career at IBM Corporation (1990-1993). He holds a B.Tech degree in Mechanical Engineering (1985) from the Indian Institute of Technology, Madras and a Direct Ph. D. (1991) in Mechanical Engineering from Cornell University. Dr. Subbarayan s research is broadly concerned with modeling and experimentally characterizing failure in microelectronic devices and assemblies. He was a pioneer in using geometric models directly for analysis, popularly referred to as Isogeometric Analysis. Among others, Dr. Subbarayan received the 2024 Richard Chu Award for Excellence in Thermal and Thermo-Mechanical Management of Electronics, 2022 SRC Technical Excellence Award, 2005 Excellence in Mechanics Award from the ASME Electronics and Photonics Packaging Division and the NSF CAREER award. He is a Fellow of ASME as well as IEEE, and he served as the Editor-in-Chief of IEEE Transactions on Advanced Packaging during 2002-2010.

Keynote III

On Scaling from Circuits to Systems.

Jairam Sukumar,

Qualcomm

Abstract - High speed interface performance has scaled up like never before. This requires a strong synergy across mixed signal circuits, platforms, software and systems. This talk will attempt to illustrate the challenges faced in co-optimization across domains to achieve the desired system performance. The talk will also focus on how such optimization approaches require innovation across domains to enable reduce system costs.

Jairam Sukumar is a Senior Director Technology at Qualcomm India. He currently leads the Mixed Signal Systems Design and Engineering IP Group. His current areas of interest include High Speed Phy Design, System Validation, Signal and Power Integrity and System PDN. He has 25 years of experience working in this industry. He completed his Masters and PhD from IISc Bangalore. He is also a Sr Member of the IEEE and has 30 publications.