Tutorial 5
Arun Chandrasekhar, Intel Corporation
The talk will start with packaging as defined by the interconnect continuum bottleneck and how packaging is a broader field compared to just the design of an IC package. We then switch to Moore's law facts vs interpretations and Heterogeneous Integration (2D, 2D+, 2.5D, 3D & 3.5D) constructs that allow package and system level scaling vs just transistor scaling.
The multi-physics aspects of packaging will be discussed with specific focus on packaging materials and the interactions between various disciplines and the engineering optimisations needed to converge on product definition. Finally, we will show examples of how an IC package nowadays is much more than just a protection of the semiconductor chip and a critical and integral part of the electrical and thermo-mechanical interconnect.
Arun Chandrasekhar Arun Chandrasekhar holds a graduate degree in Electronic Product Design from the Indian Institute of Science (IISc), Bangalore, and a Ph.D. in RF Packaging from IMEC / KU Leuven, Belgium. He joined Intel India in 2004 and has contributed to multiple data Centre CPU and GPU processor designs, spanning technology nodes from 65 nm to the current 14A generation. In addition to his industry role, Arun serves as an adjunct faculty member at IISc, Bangalore, and is a founding member of the IEEE Electronics Packaging Society (EPS) Bangalore Chapter, actively contributing to education, research, and professional community building in advanced electronics packaging.