Return2021 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Virtual Event - December 13-15, 2021 - Advance Program

Preliminary Program                                                                                                                                    All Times are China Standard Time

Monday, December 13, 2021 Tuesday, December 14, 2021 Wednesday, December 15, 2021
EDAPS TUTORIALS
Tutorial 1
Moderator:
Madhavan swaminathan, Georgia Tech

10:00 - 11:00
  • Integral Equation Methods for the Electromagnetic Analysis of Interconnect Networks: State of Art and Recent Advancements
    Shashwat Sharma and Piero Triverio
    University of Toronto
Tutorial 2
Moderator:
Thong Nguyen,University of Illinois

11:10 - 12:10
  • High-Speed Next Generation SI Challenges
    Bhyrav Mutnury
    Dell

12:20 - 13:20
Break

Tutorial 3
Moderator:
Arun Chandrasekhar, Intel

12:20 - 13:20
  • System Scaling using Waferscale Processors
    Saptadeep Pal
    UCLA
Tutorial 4
Moderator:
Madhavan Swaminathan,Georgia Tech

13:30 - 14:30
  • A Bridge Connecting Worst-Case and Statistical Eye Estimation
    Pei-Yang Weng, Tzong-Lin Wu,
    National Taiwan University

14:40 - 14:50
Day 1 Wrap Up

10:00 - 10:10
Welcome

10:10 - 10:40
Keynote Presentation
Chair:
Madhavan Swaminathan, Georgia Tech
  • Delivering Power to Modern Microprocessors
    Kaladhar Raddhakrishnan
    Intel

10:40 - 10:50
Break

10:50 - 12:30
Session 1: Design and Characterization
Chair:
TBD, TBD
  • T-I.1. A Novel Spire Clip-type Pogo Connector Design with High Electrical and Thermal Reliability [7]
    Keunwoo Kim*, Keeyoung Son*, Seokwoo Hong*, Joungho Kim*, Jinyoung Kim+
    *KAIST,
    +KET
  • T-I.2. Signal Integrity Design and Analysis of a HDMI 2.1 Connector for Improved Electrical Characteristics [15]
    Hyunwook Park*, Joonsang Park*, Gapyeol Park*, Daehwan Lho*, Boogyo Sim*, Hyungmin Kang*, Taein Shin*, Seongguk Kim*, Seonguk Choi*, Seongmin Choi+, Jinyoung Kim+ and Joungho Kim*
    KAIST,
    +KET
  • T-I.3. Novel Low Cost Launch for Measuring Via-to-Cavity coupling [32]
    Fadi Deek, Melinda Piket-May, Eric Bogatin
    University of Colorado at Boulder
  • T-I.4. Effect of Liquid Crystal Polymer on High-speed Connector Transmission Properties [19]
    Yu Bi+, Shitao Liu+, Bi Yi+ , Guoqi Zhou*, Zhongyuan Lu*,
    *AVIC Jonhon Optronic Technology,
    +ZTE Corporation
  • T-I.5. Design and Characterization of a Metamaterial Microstrip Line with Increased Effective Permittivity [57]
    Kaya Pi, Xiaofei Xu
    Shanghai University

12:30 - 12:40
Break

12:40 - 14:20
Session 2: Advanced Modeling and Simulation Techniques
Chair:
Hanzhi Ma, ZJUI
  • T-II.1. Metamodel-based prediction of On Resistance for microelectronic power switches [22]
    Georgian Nicolae*+, Andi Buzo+, Christian Feuerbaum+, Cristian Diaconu+, Horia Cucu*, Georg Pelz+, Corneliu Burileanu*
    *University Politehnica of Bucharest,
    +Infineon Technologies AG Neubiberg
  • T-II.2. Decision Feedback Equalizer (DFE) Taps Estimation with Machine Learning Methods [62]
    Bobi Shi*, Yixuan Zhao*, Hanzhi Ma+, Thong Nguyen*, Er-Ping Li+, Andreas C. Cangellaris* and Jose Schutt-Aine*
    *University of Illinois Urbana Champaign,
    +ZJU-UIUC Joint Institute, Zhejiang University
  • T-II.3. Comparison of Invertible Architectures for High Speed Channel Design [63]
    Osama Waqar Bhatti*, Oluwaseyi Akinwande*, Nikita Ambasana*, Xianbo Yang+, Pavel Roy Paladhi+, Wiren Dale Becker+, Madhavan Swaminathan*
    *Georgia Institute of Technology,
    +IBM Systems
  • T-II.4. Statistical Sensitivity Analysis in Distributed Circuits using Compact Polymorphic Polynomial Chaos Surrogates [33]
    Mohd. Yusuf, Sourajeet Roy
    Indian Institute of Technology Roorkee
  • T-II.5. A Fast method to predict the Voltage Droop for Fully Integrated Voltage Regulators in Microprocessors [59]
    Amit Kumar, Srinivasan Govindan, Srikrishnan Venkataraman
    Intel Technology India Pvt. Ltd, Bangalore, India

14:20 - 14:30
Break

14:30 - 15:30
Session 3 - Antenna Design
Chair:
Meisong Tong, Tongji Unviversity
  • T-III.1. Combining Electromagnetic Bandgap (EBG) Surface in High Gain and Low Back Radiation Antenna Design [20]
    Chun-Cheng Wang, Hung-Chih Lin, Ming-Yuan Huang, Lih-Tyng Hwang
    National Sun-Yat Sen University
  • T-III.2. The Development of Compact Patch Antenna Array with High Angular Resolution for 77GHz FMCW Radar Applications [40]
    ZhiGang Wang**, WeiHao Li*, Hongli Peng*, Changyuan Liu**, Xing Liao*
    *Shanghai Jiao Tong University,
    **Guangdong Communications & Networks Institute
  • T-III.3. A High Isolation Antenna Array with Simple Feedings for Miniaturized 35GHz Radar Applications [43]
    Shiyu Sun*, Hongli Peng*, Zhigang Wang**, Changyuan Liu**, Hong An Zhou*
    *Shanghai Jiao Tong University,
    **Guangdong Communications and Networks Institute

15:30 - 15:40
Day 2 Wrap Up

10:00 - 10:10
Welcome
10:10 - 10:40
Keynote Presentation
Chair:
Jose Schutt-Aine, University of Illinois
Keynote Title
Rajen Murugan
Texas Instruments

10:40 - 10:50
Break

10:50 - 12:30
Session 4: Power Integrity
Chair:
Xu Chen, University of Illinois
  • W-I.1. Innovative Power Integrity Analysis and Post-Silicon Co-relation for HSIOs [11]
    Mukesh Moorthy, Manjunath Jayasimha
    Intel
  • W-I.2. Impact of On-Die Inductance from top metal power delivery routings in HSIO & Ethernet [31]
    Siddhesh Arote, Manjunath Jayasimha
    Intel
  • W-I.3. Power Integrity analysis and solution for PCIE-Gen5/6 Phy [35]
    Manjunath Jayasimha, Mukesh Moorthy
    Intel
  • W-I.4. Frequency Domain Characterization Voltage Mode Buck SMPS for Power Distribution Network [60]
    Michael Chang, Simon Kao, Stephen Chu, Bryant Hsu, Mark Ciou, Choppy Lin, Robby Ho,
    HTC
  • W-I.5. Matrix-Based Evolutionary Approach for Optimization of Decoupling Capacitors [61]
    Akash Jain, Heman Vaghasiya, Jai Narayan Tripathi
    Indian Institute of Technology, Jodhpur

12:30 - 12:40
Break

12:40 - 14:40
Session 5 - Signal Integrity
Chair:
TBD, TBD

  • W-II.1. Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM) [4]
    Seongguk Kim, Taein Shin, Hyunwook Park, Daehwan Lho, Keeyoung Son, Keunwoo Kim, Joonsang Park, Seonguk Cho, Jihun Kim, Haeyeon Kim, Joungho Kim
    KAIST
  • W-II.2. Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface [12]
    Taein Shin, Hyunwook Park, Keunwoo Kim, Seongguk Kim, Keeyoung Son, Kyungjune Son, Gapyeol Park, Joonsang Park, Seonguk Choi, Joungho Kim
    KAIST
  • W-II.3. Optimized Crosstalk and Impedance Design for HBM3 Channels in InFO [6]
    Kuei-Ju Lin, Ruey-Beei Wu
    National Taiwan University
  • W-II.4. Modeling and Analysis of Cu-CNT Composite Through Glass Vias in 3D ICs [54]
    Ajay Kumar, Rohit Dhiman
    NIT Hamirpur
  • W-II.5. A Physical Verification Methodology for 3D-ICs Using Inductive Coupling [8]
    Tatsuo Omori, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    The University of Tokyo
  • W-II.6. DDR RF Interference in Fan-Less SoC Design [10]
    BoonPing Koh, SunYe E, Gaurav Hada, Asmah Truky
    Intel

14:40 - 15:00
TC-EDMS

15:00 - 15:40
Session 6: Microwave Applications
Chair:
Rohit Sharma, IIT Ropar
  • W-III.1. Electromagnetic Detection of Dielectric Cylinders by the Bat Algorithm [36]
    Xin Zhang+, Chunxia Yang+, Meisong Tong*,
    *Tongji University,
    +Shanghai Normal University
  • W-III.2. Wireless Power Transfer Technologies for Powering Multiple Sensor Nodes [46]
    Kexue Cui, Mengfei Chen, Libo Qian
    Ningbo University

15:30 - 15:40
Closing Session