EDAPS
EDAPS

EDAPS

EDAPS

EDAPS
EPS


EDA Track


Special Session on EDA Tools: Turnkey Solutions for Heterogeneous Packaging Design & Modeling

Presentation 1


An Innovative Advanced Packaging Approach That Boosts Device Miniaturization
Anna Fontanelli, Founder & CEO, MZ Technologies

Anna is a silicon executive bringing extensive know-how and more than 35 years of hands-on experience in the research, design and industrialization of innovative EDA solutions in the deep submicron silicon technologies space, having worked at Mentor Graphics, where she led the Marketing team who developed I/O Designer and at STMicroelectronics Central R&D, where she led the development, and the deployment of 3 generation of IC & Package co-design tools. In 2015, she funded Monozukuri, a European EDA company, delivering design tools and technology for next-generation vertically stacked and modularly packaged electronic products. Anna holds a master degree in Mathematics from the Universita degli studi di Milano, Italy and is the author/co-author of several papers (11 regular + 1invited) and patents (2).



Presentation 2


Next Generation Package design with Chip Package Codesign Methodology
Tejkiran Patil, Ansys

Tejkiran Patil (Senior Application Engineer, Electronics) joined Ansys in 2021 and he is specialized in SI/PI, RF domain, System level simulations and mission-based simulation methodologies. His expertise is in MIMO area, Multibeam antennas design as well as RF components design and optimization. Prior to joining Ansys, Tej has 5 years of experience in medical and defense RF & Microwave technologies. Tej has also explored system integration and testing domain. Tej received M. Tech in Electronics and Communications from Dr. Babasaheb Ambedkar Technological University, Lonere in 2016.



Presentation 3


Challenges and Opportunities as Chips Transform into Systems
John Park, Product Management Group Director for Advanced IC Packaging, Cadence Design Systems


John Park is Product Management Group Director for Advanced Semiconductor Packaging at EDA industry leader Cadence Design Systems, where he leads a team responsible for defining cross-domain solutions and methodologies for IC, package, and PCB co-design and analysis. His team primarily focuses on developing tools and flows for chiplet-based 3D designs. He has over 40 years of experience in the EDA field and is regarded as an international expert on chiplets, advanced packaging, and heterogenous integration.

Presentation 4


Pre-layout early-stage workflows for signal integrity analysis and thermal analysis for Chiplet-based designs
Subramanian Lalgudi, Siemens

Subramanian Lalgudi is a multi-physics solutions architect at Siemens EDA where he focuses on emerging areas such as 3-D ICs and power electronics. A leader in engineering simulations, he previously managed circuit simulation R&D at Ansys. He has presented at many conferences including the International Integrated Reliability Workshop and the Conference on Electrical Performance of Electronic Packaging (EPEPS) and has 11 publications including an article in IEEE Transactions on Components, Packaging, and Manufacturing Technology. He earned a PhD in electrical engineering from Georgia Institute of Technology.