Tutorial II

System Scaling using Waferscale Processors
Saptadeep Pal, UCLA

Abstract - Conventional computing is at a tipping point. On one hand, applications are fast emerging that have higher performance, bandwidth, and energy efficiency demands than ever before. On the other hand, the end of Dennard scaling as well as the slowdown of Moore's law diminishes the prospect of easy performance, bandwidth, or energy efficiency scaling in the future. Traditional framework of getting better performance and efficiency by developing and manufacturing large system-on-chips (SoCs) at the latest technology nodes is becoming prohibitively costly, more so for low- to medium-volume products. Moreover, fueled by the exponential growth of deep learning and big data analytics, scale-out systems composed of many SoCs are in great demand. Traditional integration technologies and methodologies of building scale-out systems, however, are failing to deliver the performance these applications demand. As a result of the above trends, future performance, power, and cost improvements cannot come from improvements in SoC technology alone. Then, how do we enable "System scaling"? To address this growing need for system scaling, my research has been focused on developing technology solutions and frameworks for system-technology co-optimization (STCO) which intersects the broad areas of computer architecture, VLSI design, and packaging. In this talk, I will discuss novel chiplet-based waferscale processor architectures, and design methodologies that would enable such architectures.

Saptadeep Pal received the B.Tech. degree in electrical engineering from IIT Patna, India, in 2015 and the M.S. and Ph.D. degrees from the University of California at Los Angeles, CA, USA, in 2017 and 2021 respectively. His research focuses on design and architecture of packageless, wafer-scale processor systems based on novel high-performance interconnect fabrics and rapid design space exploration frameworks for system-technology co-optimization. His work has been recognized through multiple awards, such as the Intel Best Student Paper award at ECTC 2017, Best Paper Nomination at DATE 2017, and the Qualcomm Innovation Fellowship 2019.