EDAPS
Tutorial IV:

Implications of Thermal Aspects on Interconnect and Packaging Technology - An Electro-Thermal Co-Design Perspective

Speakers: Surila Guglani, Rahul Kumar, Sourajeet Roy and Rohit Sharma



Abstract With the ever-increasing density of components on a chip, package, and board combined with the decreasing power budgets of modern electronic products, thermal losses and heat management have emerged as highly relevant design and reliability issues. This means that it is no longer enough for circuit designers to consider only the electrical behavior of interconnects and advanced packaging structures - rather the interplay between electrical performance, heat generation and losses, and power distribution needs to be taken into account. Therefore, a holistic approach towards packaging design has to be adopted.
In the first part of this tutorial, we will perform a qualitative examination of the impact of thermal losses and temperature variability on the electrical behavior of both conventional copper-based interconnects as well as emerging copper-graphene hybrid interconnects and purely graphene-based interconnects. In particular, the impacts of thermal effects will be studied both from the self-heating perspective (where the structure itself is the source of heat generation) as well as the external heating perspective (where external circuits lead to heat generation). This section will culminate in our exploration of how the thermal effects play a role in the overall reliability and mean time to failure of interconnects. In the second part of the tutorial, we will look as standard as well as emergent simulation techniques to statistically model the impact of thermal variability on the signal integrity performance of distributed interconnects. Roadblocks facing existing simulation techniques will be discussed followed by a brief assessment of very novel and cutting-edge simulation techniques for electro-thermal co-design optimization. Finally, the tutorial will end with a look into possible thermal management techniques.


Surila Guglani received the Bachelor's degree in Electronics and Communication Engineering from Govind Ballabh Pant University of Agriculture and Technology, Pantnagar, India in 2019. She is currently pursuing a Ph.D. degree in Electronics and Communication Engineering at the Indian Institute of Technology, Roorkee, India. She is a recipient of the Vice Chancellor's Gold Medal at the undergraduate level. Her current research interests include electronic design automation for high-speed circuits, uncertainty quantification, predictor-corrector algorithms for polynomial chaos metamodels, modeling and simulation of high-speed interconnects, stochastic modelling of CNT interconnects and machine learning


Rahul Kumar received the bachelor's degree in electronics engineering from Rashtrasant Tukadoji Maharaj (RTM) Nagpur University, Nagpur, India, in 2012, and the MTech. degree in very large-scale integration (VLSI) design and automation techniques from the National Institute of Technology Hamirpur, Hamirpur, India, in 2016. He is currently pursuing the Ph.D. degree in electrical engineering with IIT Ropar, Rupnagar, India. He is a recipient of Visvesvaraya fellowship scheme. His current research interests include the modeling and simulation of copper (Cu)-graphene hybrid on-chip interconnects, signal integrity and application of machine learning in interconnect packaging.



Sourajeet Roy (Member, IEEE) received the B.Tech. degree in electrical engineering from Sikkim Manipal University, Gangtok, India, in 2006, and the M.E.Sc. and Ph.D. degrees in electrical engineering from the University of Western Ontario, London, ON, Canada, in 2009 and 2013, respectively. From 2013 to 2019, he was an Assistant Professor with the Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA. Since 2019, he has been an Assistant Professor with the Department of Electrical and Communications Engineering, IIT Roorkee, Roorkee, India. His current research interests include signal and power integrity analysis of integrated circuits, machine learning-based electronic design automation (EDA) of electronic packaging, and uncertainty quantification of microwave/RF circuits. Dr. Roy is a member of the Technical Program Committee for the IEEE Electrical Performance of Electronic Packaging and Integrated Systems Conference and the IEEE Workshop on Signal and Power Integrity. He was a recipient of the Vice-Chancellors Gold Medal at the undergraduate level in 2006, the Queen Elizabeth II Graduate Scholarship in Science and Technology in 2012, and the Ontario Graduate Scholarship in 2012. His student has received the Best Poster Paper Award at the 23rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) in 2014. He currently serves as a reviewer for various IEEE transaction journals. He is currently an Associate Editor of the IEEE Transactions on Components, Packaging, and Manufacturing Technology


Rohit Sharma received the B.E. degree in electronics and telecommunication engineering from North Maharashtra University, India, in 2000, the M. Tech. degree in systems engineering from Dayalbagh Educational Institutes, India, in 2003 and the Ph.D. degree in electronics and communication engineering from Jaypee University of Information Technology, India, in 2009. He worked as a Post-Doctoral Fellow at the Design Automation Lab at Seoul National University, Seoul, Korea from Jan 2010 to Dec 2010. He was a Post-Doctoral Fellow at the Interconnect Focus Centre at Georgia Institute of Technology, Atlanta, USA from Jan 2011 to Jun 2012. Dr. Sharma joined the department of electrical engineering at the Indian Institute of Technology Ropar in 2012, where he is currently an Associate Professor. All along his tenure at IIT Ropar, he has initiated activities in the area of Electronic Packaging. His current research interests include design of high-speed chip-chip and on-chip interconnects, Graphene based nanoelectronic devices and interconnects, Signal and Thermal integrity in high-speed interconnects and 3D ICs/packages and application of Machine Learning in advanced packaging and systems. He is also the coordinator of the Indo-Taiwan Joint Research Centre on Artificial Intelligence and Machine Learning at IIT Ropar. He is an Associate Editor of the IEEE Transactions on Components, Packaging and Manufacturing Technology and a Program Committee member in IEEE EPEPS and IEEE EDAPS. He has been the General Co-Chair of the IEEE EDAPS in 2018. He is the Co-Chair of the IEEE EPS Technical Committee on Electrical Design, Modeling, and Simulation and is a Senior Member of the IEEE.