- W-I.1. Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Signal Integrity (SI) [45]
Keunwoo Kim, Hyunwook Park, Daehwan Lho, Minsu Kim, Keeyoung Son, Kyungjune Son, Seongguk Kim, Taein Shin, Joungho Kim
KAIST
- W-I.2. Policy Gradient Reinforcement Learning-based Optimal Decoupling Capacitor Design Method for 2.5-D/3-D ICs using Transformer Network [54]
Hyunwook Park, Minsu Kim, Subin Kim, Seungtaek Jeong, Seongguk Kim, Hyungmin Kang, Keunwoo Kim, Keeyoung Son, Gapyeol Park, Kyungjune Son, Taein Shin, Joungho Kim
KAIST
- W-I.3. Deep Reinforcement Learning-based Interconnection Design for 3D X-Point Array Structure Considering Signal Integrity [59]
Kyungjune Son, Minsu Kim, Hyunwook Park, Shinyoung Park, Gapyeol Park, Daehwan Lho, Seoungguk Kim, Taein Shin, Keeyoung Son, Keunwoo Kim, Joungho Kim
KAIST
- W-I.4. Gaussian Process surrogate model for variability analysis of RF circuits [81]
Thong Nguyen, Jose Schutt-Aine
UIUC
- W-I.5. Invertible Neural Networks for Inverse Design of CTLE in High-speed Channels [83]
Majid Ahadi Dolatsara*, Huan Yu*, Madhavan Swaminathan*, Jose Hejase+, Wiren Dale Becker**,
*GaTech,
+NVIDIA,
**IBM
- W-I.6. Application of Different Learning Methods for the Modelling of Microstrip Characteristics [97]
Nastaran Soleimani, Riccardo Trinchero, Flavio Canavero
Politecnico di Torino
- Live Q&A
Panel of Presenters
