- W-I.1. Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk [45] KAIST
- W-I.2. Policy Gradient Reinforcement Learning-based Optimal Decoupling Capacitor Design Method for 2.5-D/3-D ICs using Transformer Network [54] (Student Competition) KAIST
- W-I.3. Deep Reinforcement Learning-based Interconnection Design for 3D X-Point Array Structure Considering Signal Integrity [59] (Student Competition) KAIST
- W-I.4. Gaussian Process surrogate model for variability analysis of RF circuits [80] UIUC
- W-I.5. Invertible Neural Networks for Inverse Design of CTLE in High-speed Channels [82] *GaTech,
+NVIDIA,
**IBM - W-I.6. Application of Different Learning Methods for the Modelling of Microstrip Characteristics [96] (Student Competition)Politecnico di Torino
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