Tuesday, December 15

Session T-II: Signal and Power Integrity

12:30 - 14:30 - China Standard Time

Chair: Yang (Victoria) Shao, University of Illinois

  • T-II.1. Multi-physics challenges with Integrated VoltageRegulator based Power Delivery Architectures [17]
    Venkatesh Avula, Bidyut Bhattacharyya, Vanessa Smet, Yogendra Joshi, Madhavan Swaminathan
    Georgia Institute of Technology
  • T-II.2. Effective Segmentation approach of Package-to-PCB modeling using Full-Wave EM field Solver [42]
    Hansel Dsilva, Abhishek Jain, Sasikala J, Amit Kumar
    Achronix Semiconductor
  • T-II.3. High Signal Integrity Transmission Line Using Microchip Capacitors and Inductors [43] (Student Competition)
    Takahiko Kano, Moritoshi Yasunuga
    University of Tsukuba
  • T-II.4. A Large-Signal Method for Modeling Vccin feedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators [68]
    Srinivasan Govindan*+, Krishna Bharath+, Srikrishnan Venkataraman*, Dipanjan Gope**
    *Intel, Bangalore
    +Intel, Chandler
    **Indian Institute of Science
  • T-II.5. Power Distribution Network Optimization for On-Die Regulator with Laplace Transform Technique [81]
    Michael Chang
  • T-II.6. Fast Power Integrity Analysis of PDNs with Arbitrarily Shaped Power-Ground Plane Pairs [51]
    Ihsan Erdin*, Ram Achar+
    +Carleton University.
  • Live Q&A
    Panel of Presenters